1. Field of the Invention
The present invention relates to filling contact holes in a semiconductor substrate and, more specifically, to a selective deposition technique for filling contact holes and planarizing the surface at the same time.
2. Prior Art
As packing density of integrated circuits increases in very large scale integration (VLSI) technology, the need for planarization becomes more and more important. In the manufacture of silicon semiconductor devices, a variety of processes for filling contact holes are well known in the technology. The primary concern is the degradation of the junction integrity contact structure. Additionally, specific contact resistivity should be below 1.times.10.sup.-6 ohms cm.sup.2. This lower specific resistivity is essential for better device performances. For NMOS(n-channel metal oxide semiconductor) and PMOS (p-channel metal oxide semiconductor) processes, an in-situ doped polysilicon plug can be used for contact hole filling. However, in CMOS (complimentary metal oxide semiconductor) processing, the use of in-situ doped polysilicon contact plugs requires additional masking steps. These additional steps increase processing complexities.
Polysilicon can also be doped by ion implantation. The dosage and energy requirements to dope thick polysilicon plugs are not compatible with other requirements, such as the integrity of the thick dielectric film. Further, the extended high temperature anneals required to diffuse the dopant over the entire silicon plug are unacceptable.
For CMOS technology, selective tungsten deposition or tungsten etch back techniques are among the most promising ones. However, these processes have several technological problems which prevent their use within the current technology framework. When using a selective tungsten plug, the junction integrity degrades and specific contact resistivity of such structures generally exceeds 1.times.10.sup.-6 ohms cm.sup.2. The complexity of etch back processes prohibits their use. Further, the current processes are not cost efficient.
As can be seen by the present technology, obtaining low contact resistance and conformal contact hole filling at the same time is very difficult and is one of the most serious problems in present integrated circuit processing.
The present invention describes a novel process which eliminates the junction integrity problem associated with existing contact fill processes and is CMOS compatible. Further, complete planarization of the contact hole and low contact resistance can be obtained at the same time. Additionally, the thick contact hole plugs produced with this process, act as diffusion barriers between aluminum (Al) and the substrate. This barrier prevents the spiking phenomenon which leads to junction degradation.